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Design-verification work leads; cloud, embedded and full-stack systems show the range. Every project opens a case study — or names why it's closed.

Silicon · DV · 2026Verified

I2C Protocol UVM Verification

Full UVM 1.2 verification of an I2C slave controller (7-bit address, 8-register bank, clock stretching) with master BFM, dual-direction agents, and a self-checking scoreboard with shadow register bank. 17 functional covergroups, ~89 coverage points, 7 SVA protocol assertions, 18 directed/random/stress tests. 16 RTL bugs found and fixed; 95%+ predicted coverage closure.

16
Bugs found & fixed
17
Covergroups
95%+
Predicted closure
SystemVerilogUVM 1.2I2CSVAFunctional CoverageBFM
i2c_env (UVM 1.2)MASTER AGENTdriver · monitorsequencer (BFM)SLAVE AGENTPASSIVE by defaultmonitor onlySCOREBOARDshadow regs · addr ACK · data integrity · txn countCOVERAGE17 covergroups · ~89 points · 95%+ predictedDUTi2c_slaveaddr 0x508 reg bank
Silicon · DV · 2026Verified

AXI4-Lite 4×4 Crossbar UVM Testbench

Full UVM 1.2 environment for a 4-master × 4-slave AXI4-Lite crossbar with round-robin arbitration and DECERR handling. Order-tolerant scoreboard, reference model, functional coverage, and 8 directed/stress tests covering simultaneous-write, RAW hazard, starvation, and unmapped-address corners. 25 bugs identified and fixed.

25
Bugs found & fixed
8
UVM tests
Yes
RAL + refmodel
SystemVerilogUVM 1.2AXI4-LiteRALScoreboardEDA Playground
M0M1M2M3S0S1S2S3CROSSBAR4×4 fully-connectedround-robin arbiterDECERR on unmappedMASTERSSLAVES

ALSO IN THE PORTFOLIO

Silicon RTL, cloud infrastructure, embedded firmware and full-stack systems — the breadth around the verification core.

Silicon · RTL + DVVerified

AMBA SoC — AXI / AHB / APB Interconnect

Synthesizable AMBA system-on-chip: AXI crossbar, AHB decoder, APB bridge, and UART / GPIO / Timer / SPI peripherals — 11 RTL modules. Hierarchical testbench with AXI/AHB/APB protocol assertions; compiles clean under Verilator -Wall with 23 passing tests.

SystemVerilogAXI / AHB / APBVerilatorSVA
2026View
Silicon · FPGAHardware

Synchronous FIFO on Spartan-6

Parameterized synchronous FIFO (configurable depth and width) taken RTL → UVM → FPGA. Layered SystemVerilog testbench, 3 SVA properties that caught 2 flag bugs during bring-up, >95% functional coverage, and a Spartan-6 bitstream with button-debounce + 7-segment demo wrapper.

Verilog HDLUVM 1.2SVASpartan-6 FPGA
2026View
Silicon · RTLVerified

FSM Controller with Assertion-Based Verification

Multi-state Mealy/Moore FSM in SystemVerilog using strict 3-block coding style. SVA assertions verify transition correctness, output timing, and corner cases — reset during active state, illegal-state recovery, and back-to-back transitions.

SystemVerilogFSMSVASynthesizable RTL
2026View
Cloud · AI × SiliconDemo

SiliconScribe — AI-Driven RTL & Verification

Type a hardware design in plain English → an LLM generates synthesizable Verilog + a testbench → Icarus Verilog simulates it → a self-correction loop feeds compile/test errors back until it passes. FastAPI backend, React/TypeScript frontend with live SSE agent trace, VCD waveform rendering, and a fully offline curated-design mode (no API key needed).

PythonFastAPIReactLLM
2026View
Cloud · DevOpsShipped

Serverless CI/CD Pipeline (AWS)

End-to-end AWS-native CI/CD: GitHub → CodePipeline → CodeBuild (test + build) → CloudFormation/SAM deploy to Lambda + API Gateway + DynamoDB, with CloudWatch alarms and SNS notifications. Multi-environment (dev/staging/prod), pytest unit tests, and SAM local integration testing — all inside the AWS Free Tier.

AWSCodePipelineSAMCloudFormation
2026View
Cloud · IaCShipped

Terraform AWS Infrastructure

Reusable infrastructure-as-code modules provisioning AWS resources with Terraform — networking, IAM least-privilege roles, and serverless compute — written to be composable, repeatable, and version-controlled rather than click-ops.

TerraformAWSIaCIAM
2026View
Cloud · InternshipShipped

Intelligent Document Engine

Document-processing dashboard built during my Kudos Technolabs cloud internship: secure pre-signed S3 upload, Textract OCR extraction, searchable results, analytics, and report generation. Applied verification discipline — test plans, IAM least-privilege, failure injection — to cloud infrastructure.

AWSS3TextractLambda
2025View
Embedded · DSPHardware

Audio Spectrum Analyzer (STM32 Bare-Metal)

Real-time 8-band spectrum visualizer on bare-metal STM32F411. I2S MEMS-mic capture via double-buffered DMA, 512-point CMSIS-DSP FFT, Hanning windowing, automatic gain control, and dirty-rect rendering on an SSD1306 OLED at ~24 FPS. Watchdog + HardFault recovery; builds clean with the resource budget met.

STM32Embedded CCMSIS-DSPI2S
2026View
Embedded · FPGA / SDRVerified

Multiplier-less BPSK Modulator (FPGA SDR)

Hardware-efficient BPSK modulator on Spartan-6: a single DDS core with phase-shift-via-XOR (no multipliers, no DSP48, no BRAM) feeding three backends — square wave, 8-bit parallel DAC, and 1-bit sigma-delta. Pipelined for Fmax headroom. Self-checking testbench demodulates 59 bits over 100 carrier periods with zero errors.

VerilogFPGADDSSDR
2026View
Embedded · Android / RFShipped

WiRadar — WiFi Diagnostic Suite (Android)

Android app for WiFi network analysis: a 60 FPS radar canvas with phosphor decay, 5-factor scoring, threat detection (Evil Twin, Rogue AP, Deauth Flood), channel-occupancy view, walk-test heatmaps, and PDF report export. Zero-allocation render loop, MVVM + Hilt + Room, privacy-first (no cloud, all local).

KotlinAndroid CanvasMVVMHilt
2026View
Embedded · AVRHardware

Ultrasonic Distance Measurement (AVR)

Interrupt-driven distance measurement on AVR ATmega32 with an HC-SR04 sensor. External interrupts (INT0/INT1) for echo capture, 16-bit Timer1 input-capture for precise pulse-width timing, a register-level LCD driver, and UART telemetry at 9600 baud.

AVR ATmega32Embedded CInterruptsTimer Capture
2025View
Web · Full-stackShipped

MLBB Stats — Full-Stack Companion App

Next.js + TypeScript companion for a mobile game: 60+ hero tier list, dynamic hero detail pages, and a Draft Assistant whose weighted scoring engine recommends picks/bans live as the draft state changes. Build-time data pipeline with 8-way concurrent fetch, retries, and a 24h cache; strict TypeScript throughout.

Next.jsTypeScriptTailwindData Pipeline
2026View