Synchronous FIFO on Spartan-6

Parameterized synchronous FIFO (configurable depth and width) taken RTL → UVM → FPGA. Layered SystemVerilog testbench, 3 SVA properties that caught 2 flag bugs during bring-up, >95% functional coverage, and a Spartan-6 bitstream with button-debounce + 7-segment demo wrapper.