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Silicon · RTL + DV · 2026Verified

AMBA SoC — AXI / AHB / APB Interconnect

Synthesizable AMBA system-on-chip: AXI crossbar, AHB decoder, APB bridge, and UART / GPIO / Timer / SPI peripherals — 11 RTL modules. Hierarchical testbench with AXI/AHB/APB protocol assertions; compiles clean under Verilator -Wall with 23 passing tests.

Local repo — walkthrough available on request
11
RTL modules
23
Tests passing

// stack

SystemVerilogAXI / AHB / APBVerilatorSVARTL

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