All work
Silicon · DV · 2026Verified

AXI4-Lite 4×4 Crossbar UVM Testbench

Full UVM 1.2 environment for a 4-master × 4-slave AXI4-Lite crossbar with round-robin arbitration and DECERR handling. Order-tolerant scoreboard, reference model, functional coverage, and 8 directed/stress tests covering simultaneous-write, RAW hazard, starvation, and unmapped-address corners. 25 bugs identified and fixed.

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EDA Playground
25
Bugs found & fixed
8
UVM tests
Yes
RAL + refmodel

// architecture

M0M1M2M3S0S1S2S3CROSSBAR4×4 fully-connectedround-robin arbiterDECERR on unmappedMASTERSSLAVES

// the work

Dual-target flow: QuestaSim/ModelSim via Makefile regression, plus a flat-file Riviera-PRO build for EDA Playground. Master and slave agents, virtual sequencer, configuration object, RAL register model, and five documented bug categories (interface-in-package, UVM phase misuse, multi-driver loops, scoreboard race demotion, refmodel ordering).

// stack

SystemVerilogUVM 1.2AXI4-LiteRALScoreboardEDA Playground

// related writeups

Closing Coverage on an I2C UVM Testbench — 89 Points, 17 Covergroups25 Bugs in an AI-Generated AXI4-Lite Crossbar — A Debug Walkthrough
Next projectAMBA SoC — AXI / AHB / APB Interconnect