Debug walkthroughs, coverage-closure notes, and RTL bug post-mortems — public on GitHub.
- May 12, 2026
Closing Coverage on an I2C UVM Testbench — 89 Points, 17 Covergroups
Analytical coverage closure assessment. Expanded an 8-covergroup model to 17 with cross-coverage, traced every bin to a directed/random test, identified 5 documented holes, and predicted 95%+ closure without a local simulator. The methodology, not just the numbers.
UVMFunctional CoverageSystemVerilog - May 12, 2026
25 Bugs in an AI-Generated AXI4-Lite Crossbar — A Debug Walkthrough
Took an AI-drafted AXI4-Lite crossbar testbench from compile-broken to fully verified. Five debug lessons: interface-in-package, multi-driver loops, scoreboard race demotion, refmodel ordering, UVM phase misuse. Every fix traced to a root cause, not a patch.
AXI4-LiteUVMDebugBug Analysis - May 11, 2026
I2C Slave Controller — 16 RTL Bugs, 9 Categories, Documented
Full bug report from a faculty-led I2C UVM verification project. Critical issues: shift register capturing ACK as data, TX mode driving high-Z, clock-stretch returning to wrong state, SCL stuck-low in master. Every bug with severity, repro, and the fix that landed.
I2CRTL DebugVerificationSystemVerilog