Kushal Pitaliya — VLSI Design Verification Engineer

KUSHAL

PITALIYA

Engineer · Builder · Creator

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Open to VLSI / Design Verification roles

Design Verification Engineer

I find bugs in silicon before silicon finds them in production — and build the cloud & embedded systems around the work.

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Verification output · Internship 2026

41+Bugs found & fixedacross two UVM testbenches

89+Coverage pointsacross 17 functional covergroups

2Protocols verifiedI2C (UM10204) + AXI4-Lite

10+Public repossilicon, cloud & embedded

NOW — week of May 16, 2026

Closing the remaining coverage holes on the I2C UVM testbench — stretch×read (CG17) and rep_dir×WRITE (CG14). Targeting 17/17 covergroup closure by end of week.

next.commit →github.com/k-pitaliya/i2c-protocol-dv

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Two verification environments, in depth. The full silicon · cloud · embedded gallery lives on the work page.

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Silicon · DV · 2026

I2C Protocol UVM Verification

Full UVM 1.2 verification of an I2C slave controller (7-bit address, 8-register bank, clock stretching) with master BFM, dual-direction agents, and a self-checking scoreboard with shadow register bank. 17 functional covergroups, ~89 coverage points, 7 SVA protocol assertions, 18 directed/random/stress tests. 16 RTL bugs found and fixed; 95%+ predicted coverage closure.

AXI4-Lite 4×4 Crossbar UVM Testbench

Full UVM 1.2 environment for a 4-master × 4-slave AXI4-Lite crossbar with round-robin arbitration and DECERR handling. Order-tolerant scoreboard, reference model, functional coverage, and 8 directed/stress tests covering simultaneous-write, RAW hazard, starvation, and unmapped-address corners. 25 bugs identified and fixed.

// the engineer

Design Verification — built to find bugs

I'm Kushal Pitaliya, an ECE undergrad at CHARUSAT. Digital electronics clicked for me from day one — the idea that logic gates, clock domains, and timing constraints could build real intelligence into silicon felt more concrete than any other branch of engineering.

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