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KUSHAL
PITALIYA

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Kushal Pitaliya — VLSI & Cloud Engineer Portfolio

Open to VLSI & Cloud roles · 2026

KUSHALPITALIYA

I design silicon and architect the cloud

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01

AboutMe

KPVLSI · Cloud Engineer

I'mKushalPitaliyafromB.Techdayone,digitalelectronicsmadethemostsensetome.Theideathatlogicgates,clocking,andtimingconstraintscouldbuildrealintelligenceintosiliconalwaysfeltmoretangiblethantheory.ThatcuriositypushedmetowardFPGAprojects,thentowardharderquestionsaboutthoseprojects.

BuildingaFIFOonhardwarewasonething.Provingitwascorrectsystematically,acrossthousandsofscenariosInevermanuallythoughtofthat'swhatledmetoVLSIDesignVerification.InowdesignandverifyRTLinSystemVerilog,writeUVM1.2testbencheswithfunctionalcoverage,andprototypeonSpartan-6FPGAs.

Onthecloudside,IarchitectserverlesspipelinesonAWSLambda,Textract,DynamoDB,APIGatewayshippedaproductiondocumentprocessingengineduringmyinternshipatKudosTechnolabs.Ibelieveinfrastructureshouldbeasrigorouslyverifiedassilicon.Goodengineersbuildthings.Greatengineersprovetheirthingswork.

0+RTL & Cloud Projects
0+Technologies
0+CGPA
02

Skills&Technologies

Verilog HDL / VHDLExpert
SystemVerilog / SVAAdvanced
RTL Design & SynthesisAdvanced
UVM 1.2 MethodologyProficient
Functional CoverageProficient
FPGA Prototyping (Xilinx ISE/Vivado)Advanced
03

FeaturedProjects

01
AEP
vlsi

AI-Driven EDA Playground

Browser-based RTL design environment where natural language prompts generate Verilog modules, auto-generate testbenches, run simulation via Icarus Verilog, and self-correct bugs autonomously.

SystemVerilogAI/LLMIcarus VerilogNext.jsPython
02
SFMB
vlsi

Synchronous FIFO Memory Buffer

Hardware-verified 8-bit Synchronous FIFO on Xilinx Spartan-6 FPGA with robust signal debouncing, power-on reset logic, and real-time status monitoring. Directed and randomized testbenches.

Verilog HDLSpartan-6 FPGAXilinx ISETestbench
03
FDC
vlsi

FSM-Based Digital Controller

Multi-state Mealy/Moore FSM in SystemVerilog with clock-driven structured testbenches and assertions. Strictly synthesizable with always_ff/always_comb constructs and full coverage.

SystemVerilogFSMSVA AssertionsSynthesis
04
ASA
embedded

Audio Spectrum Analyzer

Real-time 8-band spectrum visualizer on bare-metal STM32. Captures audio via I2S MEMS mic, processes with 512-point FFT (CMSIS-DSP), applies AGC, and renders on SSD1306 OLED at ~24 FPS.

STM32Embedded CCMSIS-DSPI2SDMAOLED
05
UDM
embedded

Ultrasonic Distance Measurement

Real-time distance measurement using AVR ATmega32 with HC-SR04 sensor. Interrupt-driven echo detection, Timer1 input capture for precision, custom LCD driver, and UART serial output.

AVREmbedded CUARTTimersInterrupts
06
CSA
web

Control System Analyzer

Interactive web tool for control system analysis — step/impulse/ramp responses, Bode/Nyquist/Polar plots, Root Locus, and Routh-Hurwitz stability. 24 unit tests with Vitest.

JavaScriptViteChart.jsMathJaxVitest
07
SS2
web

Semiconductor Summit 2.0

Full-stack event website for a semiconductor conference with React + Vite frontend and Node.js/MongoDB backend. Automated PDF receipt parsing, role-based dashboards, and email automation.

ReactViteNode.jsMongoDBNodemailerREST API
08
SCP
cloud

Serverless CI/CD Pipeline

Task Manager REST API with fully automated CI/CD: GitHub → CodePipeline → CodeBuild → CloudFormation → Lambda + API Gateway + DynamoDB. CloudWatch alarms and SNS notifications included.

AWS LambdaAPI GatewayDynamoDBSAMCodePipelinePython
09
IDPE
cloud

Intelligent Document Processing Engine

Fully serverless OCR pipeline: S3 uploads trigger Lambda → AWS Textract extracts structured data → DynamoDB stores metadata → SNS notifies downstream. IAM least-privilege throughout.

AWS TextractLambdaS3DynamoDBSNSPython
10
CIaC
cloud

Cloud Infrastructure as Code

Reusable Terraform modules for VPC, EC2, S3, and IAM. Remote state backends with DynamoDB locking, variable-driven multi-environment configs, and CI-validated terraform plan.

TerraformAWSVPCEC2S3IAM
11
t(P
other

text-parsematch (PyPI Package)

Published Python package for processing text inputs with pattern matching, retry mechanisms, and schema validation. Returns structured and validated outputs for data extraction workflows.

PythonPyPIPattern MatchingSchema Validation

11 projects · scroll to explore

04

Experience

May 2025 — July 2025

Cloud Technologies Intern

Kudos Technolabs

01
  • Designed and developed an Intelligent Document Processing Engine using AWS Lambda, Textract, DynamoDB, API Gateway, and S3
  • Built a fully functional frontend dashboard with file upload, real-time analytics, dynamic report generation, and search/filter capabilities
  • Automated extraction and analysis of text data from PDF and image documents using Amazon Textract
  • Delivered a self-driven project end-to-end — from architecture planning to deployment within the AWS Free Tier
Jul 2025 — Present

Undergraduate Student Fellow (UGSF)

CHARUSAT — ECE Department

02
  • Merit-based fellowship focused on digital design, FPGA development, and embedded systems research
  • Led hands-on workshops covering Verilog RTL design, FPGA prototyping on Xilinx, and PCB layout techniques
  • Organized technical talks and managed events end-to-end — coordinating between speakers, student teams, and faculty
  • Participated in iChip 3.0 Verilog Hackathon — collaborative RTL design challenge with timed problem-solving
05

Education

2023 — Present

GPA: 8.74 / 10

Charotar University of Science and Technology (CHARUSAT)

Bachelor of TechnologyElectronics & Communication Engineering

Key Coursework

Digital VLSI DesignDesign, Testing & VerificationComputer ArchitectureEmbedded SystemsSignal ProcessingData Structures & Algorithms

Achievements

  • Undergraduate Student Fellow (UGSF) — Merit-based selection for digital design research
  • iChip 3.0 Verilog Hackathon — RTL design challenge participant
  • Second Runner-up — Idea Show 3.0
  • Odoo x CHARUSAT Hackathon 2025 — Participant
2021 — 2023

GPA: JEE: 93 percentile · 10th: 83%

Shree G.K. Dholakiya School

Higher Secondary (12th)Science — Gujarat Board

06

Certifications

Design of Digital Circuits with VHDL Programming

L&T EduTech

2024

Undergraduate Student Fellow (UGSF)

CHARUSAT

2024

AWS Cloud Technical Essentials

Coursera

2025

Design of Digital Circuits with VHDL Programming

L&T EduTech

2024

Undergraduate Student Fellow (UGSF)

CHARUSAT

2024

AWS Cloud Technical Essentials

Coursera

2025

Google AI Essentials Specialization

Google

2025

Google Cloud Essentials

Google Cloud

2025

Google AI Essentials Specialization

Google

2025

Google Cloud Essentials

Google Cloud

2025
07

Blog&Writing

01
Mar 10, 2025·4 min read
SystemVerilogVerilogVLSIVerification

From Verilog to SystemVerilog: A Practical Transition Guide

What I learned moving from basic Verilog to SystemVerilog — always_ff vs always_comb, interfaces, SVA assertions, and why it matters for modern design verification workflows.

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02
May 20, 2025·4 min read
VerilogFPGASpartan-6Xilinx ISE

Building a Synchronous FIFO: From RTL to FPGA Verification

A deep dive into designing, simulating, and hardware-verifying an 8-bit FIFO on Spartan-6 — signal debouncing, power-on reset, directed testbenches, and lessons learned.

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03
Jun 15, 2025·4 min read
STM32Embedded CDSPBare-Metal

Building a Bare-Metal Audio Spectrum Analyzer on STM32

How I built an 8-band real-time spectrum visualizer from scratch — I2S microphone, CMSIS-DSP FFT, AGC, and SSD1306 OLED rendering at 24 FPS on a $5 microcontroller.

Read More
08

WhatPeopleSay

Kushal shows exceptional depth in digital design — his FIFO buffer implementation on Spartan-6 and FSM verification work demonstrate an understanding of RTL methodology well beyond his academic level. A strong candidate for VLSI design roles.

DKK

Dr. Ketan Kotecha

Professor & UGSF Faculty Advisor, CHARUSAT ECE

09

GetInTouch

Have an idea? Let's turn it
into reality.

Let's build something together

I'm always open to new opportunities and interesting projects. Feel free to reach out!

pitaliyakushal@gmail.com