KP
KUSHAL
PITALIYA

Engineer · Builder · Creator

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Open to VLSI / Design Verification roles

Kushal Pitaliya

Design Verification Engineer

I find bugs in silicon before silicon finds them in production.

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Verification output · Internship 2026

0+Bugs found & fixedacross two UVM testbenches
0+Coverage pointsacross 17 functional covergroups
0+UVM componentsdrivers, monitors, scoreboards, sequences
0Protocols verifiedI2C (UM10204) + AXI4-Lite
Current focus · week of May 16, 2026

Closing the remaining coverage holes on the I2C UVM testbench — stretch×read (CG17) and rep_dir×WRITE (CG14). Targeting 17/17 covergroup closure by end of week.

next.commit →github.com/k-pitaliya/i2c-protocol-dv
02 / Selected

Selected Work

Featured UVM verification environments. Each case study links to source, EDA Playground flow, and the engineering writeup.

FEATURED · MAY 2026

AXI4-Lite 4×4 Crossbar UVM Testbench

Full UVM 1.2 verification environment for a 4-master × 4-slave AXI4-Lite crossbar with round-robin arbitration and DECERR handling. Order-tolerant scoreboard, reference model, functional coverage, and 8 directed/stress tests covering simultaneous-write, RAW hazard, starvation, and unmapped-address corners. Full rewrite May 2026 — 25 bugs identified and fixed.

25
Bugs found & fixed
8
UVM tests
3
Coverage groups
SystemVerilogUVM 1.2AXI4-LiteScoreboardReference ModelEDA Playground
View RepoEDA Playground
M0M1M2M3S0S1S2S3CROSSBAR4×4 fully-connectedround-robin arbiterDECERR on unmappedMASTERSSLAVES
FEATURED · MAY 2026

I2C Protocol UVM Verification

Full UVM 1.2 verification of an I2C slave controller (7-bit address, 8-register bank, clock stretching) with master BFM, dual-direction agents, and self-checking scoreboard with shadow register bank. 17 functional covergroups, ~89 coverage points, 7 SVA protocol assertions, and 18 directed/random/stress tests. 16 RTL bugs identified and fixed; 95%+ predicted coverage closure.

16
Bugs found & fixed
17
Covergroups
95%+
Predicted closure
SystemVerilogUVM 1.2I2CSVAFunctional CoverageBFM
View RepoEDA Playground
i2c_env (UVM 1.2)MASTER AGENTdriver · monitorsequencer (BFM)SLAVE AGENTPASSIVE by defaultmonitor onlySCOREBOARDshadow regs · addr ACK · data integrity · txn countCOVERAGE17 covergroups · ~89 points · 95%+ predictedDUTi2c_slaveaddr 0x508 reg bank
FEATURED · MAY 2026

FSM Controller with Assertion-Based Verification

Multi-state Mealy/Moore FSM in SystemVerilog using strict 3-block coding style (state register, next-state logic, output logic). SVA assertions verify state transition correctness, output timing, and corner cases (reset during active state, illegal-state recovery, back-to-back transitions).

SystemVerilogFSMSVASynthesizable RTL
View Repo
IDLELOADEXECDONESVA bind on transitions
FEATURED · MAY 2026

Synchronous FIFO on Spartan-6

Parameterized synchronous FIFO with configurable depth and data width, hardware-verified on Xilinx Spartan-6 FPGA. Layered SystemVerilog testbench with separate driver, monitor, and checker. Directed and randomized stimulus for full/empty boundary, pointer wraparound, and back-to-back burst stress.

Verilog HDLSystemVerilog TBSpartan-6 FPGAXilinx ISE
View Repo
// diagram pending
FEATURED · MAY 2026

Audio Spectrum Analyzer (STM32 Bare-Metal)

Real-time 8-band spectrum visualizer on bare-metal STM32F411. Captures audio via I2S MEMS mic, processes with 512-point CMSIS-DSP FFT, applies automatic gain control, and renders on SSD1306 OLED at ~24 FPS. Double-buffered DMA for zero-CPU continuous sampling.

STM32Embedded CCMSIS-DSPI2SDMAFFT
View Repo
// diagram pending

ALSO IN THE PORTFOLIO

Supporting projects across embedded and digital design.

embedded

Ultrasonic Distance Measurement (AVR)

Interrupt-driven distance measurement on AVR ATmega32 with HC-SR04 sensor. External interrupts (INT0/INT1) for echo capture, 16-bit Timer1 input-capture for precision pulse-width measurement, custom register-level LCD driver, UART telemetry at 9600 baud.

03 / Stack

Stack & Approach

The toolchain, language stack, and verification methodology I actually use.

Languages

  • SystemVerilog
  • Verilog HDL
  • C / C++
  • Python
  • GNU Make
  • Bash

Tools

  • QuestaSim
  • ModelSim
  • Riviera-PRO
  • EDA Playground
  • Xilinx Vivado / ISE
  • Git / GitHub

Methodology

  • UVM 1.2 architecture
  • Constrained-random verification
  • Coverage-driven closure
  • SVA property binding
  • Scoreboard with reference model
  • Spec → testplan → RCA workflow

I treat verification as a documentation problem first and a code problem second. A coverage report nobody can read is worse than no coverage. Every bug I've filed has a markdown RCA, every covergroup has a traced reason, every test has a spec line behind it. The methodology shows in the docs, not the LOC count.

04 / Background

Background

Experience, education, and credentials — reverse-chronological.

  1. May 2026 · PresentWork

    CHARUSAT — VLSI Summer Internship 2026

    Design Verification Intern · Faculty-led

    • Shipping two full UVM 1.2 verification environments — AXI4-Lite 4×4 crossbar and I2C slave controller — with documented bug reports, coverage closure analysis, and reproducible EDA Playground flows
    • Built reusable UVM infrastructure: virtual sequencers, layered scoreboards with reference models, per-byte coverage tracking, and SVA property libraries for protocol invariants
    • Authored verification plans and coverage closure reports; 41 RTL bugs identified and fixed across both projects
  2. Aug 2024 · PresentWork

    CHARUSAT ECE — Undergraduate Student Fellow (UGSF)

    Merit-based fellowship

    • Digital design, FPGA prototyping, and verification methodology research
    • Led hands-on workshops on Verilog RTL, Xilinx FPGA bring-up, and PCB layout for 50+ students
    • iChip 3.0 Verilog Hackathon — timed collaborative RTL design challenge
  3. May 2025 · Jul 2025Work

    Kudos Technolabs

    Engineering Intern · Cloud Track

    • Delivered a production document-processing pipeline end-to-end — architecture, implementation, deployment
    • Applied verification-style discipline (test plans, IAM least-privilege, failure injection) to cloud infrastructure
  4. 2024Cert

    Design of Digital Circuits with VHDL Programming

    L&T EduTech · Certification

  5. 2023 · 2027 (Expected)Education

    Charotar University of Science and Technology (CHARUSAT)

    B.Tech in Electronics & Communication Engineering · CGPA 8.74 / 10

    • Coursework: Digital VLSI Design · Design Testing & Verification · Computer Architecture · Embedded Systems
    • Achievements: UGSF Fellowship · Second Runner-up Idea Show 3.0 · iChip 3.0 Verilog Hackathon
  6. 2021 · 2023Education

    Shree G.K. Dholakiya School

    Higher Secondary — Gujarat Board · JEE 93 percentile

05 / Writeups

Writeups

Engineering writeups, debug walkthroughs, and coverage closure notes. Hosted on GitHub for free, public access.

06 / About

About

The story behind the verification work.

Kushal Pitaliya — VLSI Design Verification Engineer
VLSI · DV Engineer

I'mKushalPitaliya,anECEundergradatCHARUSAT.Digitalelectronicsclickedformefromdayone—theideathatlogicgates,clockdomains,andtimingconstraintscouldbuildrealintelligenceintosiliconfeltmoreconcretethananyotherbranchofengineering.

BuildingaFIFOonFPGAwasonething.Provingitcorrect—systematically,acrossthousandsofstimuliInevermanuallythoughtof—that'swhatpulledmetowardDesignVerification.IwriteSystemVerilogRTL,buildUVM1.2testbencheswithconstrained-randomstimulus,closefunctionalcoverage,andwriteSVApropertiestolockdownprotocolinvariants.

OverthelastsixmonthsI'veshippedtwofullUVMverificationenvironments—anAXI4-Lite4×4crossbar(25bugsfoundandfixed,fullrewriteMay2026)andanI2CprotocolDUT(16bugsfoundandfixed,17covergroups,~89coveragepoints,95%+predictedclosure).BothprojectshavepublishedEDAPlaygroundflowssotheworkisreproducible,notascreenshot.

07 / Contact

Contact

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Have an idea? Let's turn it
into reality.

Let's build something together

I'm always open to new opportunities and interesting projects. Feel free to reach out!

pitaliyakushal@gmail.com