01 / About

The story behind the verification work.

Kushal Pitaliya — VLSI Design Verification Engineer
VLSI · DV Engineer
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Design Verification — built to find bugs

I'm Kushal Pitaliya, an ECE undergrad at CHARUSAT. Digital electronics clicked for me from day one — the idea that logic gates, clock domains, and timing constraints could build real intelligence into silicon felt more concrete than any other branch of engineering.

Building a FIFO on FPGA was one thing. Proving it correct — systematically, across thousands of stimuli I never manually thought of — that's what pulled me toward Design Verification. I write SystemVerilog RTL, build UVM 1.2 testbenches with constrained-random stimulus, close functional coverage, and write SVA properties to lock down protocol invariants.

Over the last six months I've shipped two full UVM verification environments — an AXI4-Lite 4×4 crossbar (25 bugs found and fixed) and an I2C protocol DUT (16 bugs, 17 covergroups, ~89 coverage points, 95%+ predicted closure) — both with published EDA Playground flows. Around that core I build the tooling and infrastructure that verification runs on: AWS serverless pipelines, an LLM-driven RTL/testbench generator, and real-time embedded DSP firmware. The verification mindset travels.

02 / Stack

Four domains, one engineering discipline — the stack I build with, and the verification methodology behind it.

01 / Silicon · DV

VLSI Design Verification

  • SystemVerilog (logic, interfaces, packages, clocking)
  • UVM 1.2 (agents, sequencers, scoreboards, virtual sequences)
  • Constrained-Random Verification
  • Functional Coverage (covergroups, cross, ignore_bins)
  • SVA Assertions (immediate, concurrent, bind)
  • RTL Design (FSMs, datapath, parameterized)
  • Protocol Verification — I2C, AXI4-Lite (verified); APB/AHB (RTL)
  • Scoreboard Architecture (analysis ports, reference models)
02 / Embedded · Firmware

Embedded Systems

  • Embedded C / Bare-Metal Firmware
  • STM32 / ARM Cortex-M (HAL, LL, register-level)
  • AVR (ATmega32)
  • I2C / SPI / UART / I2S
  • Interrupts, DMA, Timers, ADC
  • CMSIS-DSP / FFT / Signal Chain
03 / Cloud · Software

Cloud & Software

  • AWS (Lambda, API Gateway, DynamoDB, S3, Step Functions)
  • Serverless — AWS SAM & CDK
  • Terraform / Infrastructure as Code
  • CI/CD (CodePipeline, GitHub Actions)
  • Python / FastAPI
  • React / Next.js / TypeScript
04 / Tooling · Build

Tools & Build

  • ModelSim / QuestaSim / Riviera-PRO
  • Xilinx Vivado / ISE (Spartan-6)
  • EDA Playground (UVM 1.2)
  • GNU Make / Regression Scripts
  • Git / GitHub / GitHub Actions
  • Linux · Bash · C · Python

Methodology in practice

Verification Methodology

  • UVM 1.2 — agents, sequencers, scoreboards, virtual sequences
  • Constrained-random + directed test strategy
  • Coverage-driven closure (functional, cross, ignore_bins)
  • SVA property binding for protocol invariants
  • Reference model + analysis-port scoreboard architecture

Tools in Practice

  • QuestaSim — full regression + UCDB merge
  • Aldec Riviera-PRO — EDA Playground mirror flow
  • ModelSim — waveform debug
  • Icarus Verilog — quick syntax + smoke runs
  • Xilinx Vivado / ISE — Spartan-6 FPGA prototyping

Workflow & Documentation

  • Spec → testplan → coverage model → regression → bug filing → RCA
  • Markdown-first bug reports (BUG_REPORT.md, FINAL_ANALYSIS_REPORT.md)
  • Coverage closure reports with bin-level traceability
  • Reproducible flows — Makefile + flat EDA Playground mirror

Languages & Build

  • SystemVerilog, Verilog HDL — RTL + testbench
  • C — embedded firmware, bare-metal
  • Python — automation, regression scripts, data tooling
  • GNU Make — multi-file builds, regression matrix
  • Git / GitHub — public repos with CI-ready structure
03 / Background

Experience, education, and credentials — one reverse-chronological rail.

  1. May 2026 · PresentWork

    CHARUSAT — VLSI Summer Internship 2026

    Design Verification Intern · Faculty-led

    • Shipping two full UVM 1.2 verification environments — AXI4-Lite 4×4 crossbar and I2C slave controller — with documented bug reports, coverage closure analysis, and reproducible EDA Playground flows
    • Built reusable UVM infrastructure: virtual sequencers, layered scoreboards with reference models, per-byte coverage tracking, and SVA property libraries for protocol invariants
    • Authored verification plans and coverage closure reports; 41 RTL bugs identified and fixed across both projects
  2. Aug 2024 · PresentWork

    CHARUSAT ECE — Undergraduate Student Fellow (UGSF)

    Merit-based fellowship

    • Digital design, FPGA prototyping, and verification methodology research
    • Led hands-on workshops on Verilog RTL, Xilinx FPGA bring-up, and PCB layout for 50+ students
    • iChip 3.0 Verilog Hackathon — timed collaborative RTL design challenge
  3. May 2025 · Jul 2025Work

    Kudos Technolabs

    Engineering Intern · Cloud Track

    • Delivered a production document-processing pipeline end-to-end — architecture, implementation, deployment
    • Applied verification-style discipline (test plans, IAM least-privilege, failure injection) to cloud infrastructure
  4. 2024Cert

    Design of Digital Circuits with VHDL Programming

    L&T EduTech · Certification

  5. 2023 · 2027 (Expected)Education

    Charotar University of Science and Technology (CHARUSAT)

    B.Tech in Electronics & Communication Engineering · CGPA 8.74 / 10

    • Coursework: Digital VLSI Design · Design Testing & Verification · Computer Architecture · Embedded Systems
    • Achievements: UGSF Fellowship · Second Runner-up Idea Show 3.0 · iChip 3.0 Verilog Hackathon
  6. 2021 · 2023Education

    Shree G.K. Dholakiya School

    Higher Secondary — Gujarat Board · JEE 93 percentile