I2C Protocol UVM Verification
Full UVM 1.2 verification of an I2C slave controller (7-bit address, 8-register bank, clock stretching) with master BFM, dual-direction agents, and a self-checking scoreboard with shadow register bank. 17 functional covergroups, ~89 coverage points, 7 SVA protocol assertions, 18 directed/random/stress tests. 16 RTL bugs found and fixed; 95%+ predicted coverage closure.
// architecture
// the work
Architecture: PASSIVE slave agent with check-before-set config_db override, per-byte ACK/NACK tracking in the monitor, and a scoreboard layering address validation, data integrity, transaction count, and NACK suppression. Coverage model spans direction, size buckets, address ranges, protocol events (START/STOP/repeated-START), ACK, byte-NACK, clock-stretch and repeat-depth, plus six cross covergroups. Dual bench: QuestaSim regression + flat Riviera-PRO build for EDA Playground.
// stack
// related writeups