All work
Cloud · AI × Silicon · 2026Working demo
SiliconScribe — AI-Driven RTL & Verification
Type a hardware design in plain English → an LLM generates synthesizable Verilog + a testbench → Icarus Verilog simulates it → a self-correction loop feeds compile/test errors back until it passes. FastAPI backend, React/TypeScript frontend with live SSE agent trace, VCD waveform rendering, and a fully offline curated-design mode (no API key needed).
// the work
The bridge between my silicon and software sides. Real simulation (iverilog -g2012, auto $dumpvars injection, VCD→SVG waveforms), per-run sandboxed execution with timeouts and path-traversal-safe artifact serving, and an honest coverage model (test-vector pass-rate, not synthesis toggle coverage).
// stack
PythonFastAPIReactLLMIcarus VerilogSSE